In conventional systems, coding of events, monitors, assertions, properties and checkers for digital circuits is a complicated process. Generally, these systems are comprised of ASICs (application specific integrated circuits), FPGAs (field programmable gate arrays) and SoCs (system on chips).
Initially, designers could design integrated circuits at the gate level. In other words, the designers would determine the particular arrangement and interconnection of logic gates (for example, NOT, OR, AND, NAND or NOR gates) which would achieve the desired functionality. The physical layout of the logic gates could then be determined and the corresponding physical device constructed.
As the size and complexity of integrated circuits (IC) has increased, various tools have been developed to assist designers in their work. For example, a USL waveform viewer shows signal values over time periods. The waveform viewer is also capable of displaying the associated USL code that generates these signals. This displayed code can be recoded, manually, as the test proceeds, or after the test is completed, for the next series of tests.
A further purpose of using a test bench is to determine the impact of signal inputs on the signal outputs. The visual medium of the USL waveform viewer substantially raises the gate level abstractive design. The abstractive design is the IC gating model. That is, greater complexity can be developed with a more visually complex review mechanism (the waveform viewer) than with other methods of design expression. The design process is simplified because the waveform viewer method is more intuitive than other methods. Intuitive methods of hardware design are generally faster. Usually USL waveform viewers are passive devices displaying signal inputs and outputs. In some designs, a limited quantity of discrete manipulation of individual source signal inputs is possible.
However, as circuit design geometrically increases in complexity and design, the sheer number of elements, even for repetitive use gates, requires substantial amounts of manual coding resources. This necessarily leads to longer product development cycles and higher unit costs.
At the behavioral level, a circuit or sub-component of a circuit can be described in terms of the inputs to the circuit, the outputs from the circuit, and the processes which are performed by the circuit, thereby transforming the input signals into the output signals. The behavioral characterization of the circuit is normally provided through a USL software component.
A USL behavioral description is coded software of how a digital system works. This description is essentially a “black box” with a certain set of inputs and a certain set of outputs. The manner in which the outputs are generated from the inputs is described functionally, but not in terms of the specific arrangement of logic gates within the IC under development. The USL behavioral description is transformed into a gate level structural description of the circuit by a synthesis tool. The synthesis tool reads the USL behavioral description and generates a corresponding description which consists of a list of logic gates and the interconnections between the gates.
The development of increasingly sophisticated developer toolkits contained within waveform viewer test benches (the physical and logical device that connects the integrated circuit to the test inputs and results outputs) has not come with a parallel increase in lessening the demands of manual coding. Generally, input signals are not compared to each other, only to the output signals displayed in a waveform viewer or some other display means. The outputs are always derived from inputs made to the subject device through a test bench process. In other words, each design, from the gate-level upward, requires completely fresh coding, though the essential function remains the same.
USL code was specifically developed for advanced generation IC design. The USL languages contain greater amounts of information in fewer lines of code. This is particularly important as the complexity of digital circuits requires increasing the number of processor instruction sets. Fewer lines of code also reduce the number of errors in the total code.
Although the code language is more sophisticated, and results in less code density, it is necessary to have a better means of identifying which line of code affects what part of the gate design. Faster identification of the erroneous code at the beginning of the instruction set or routine leads to fewer subsequent errors. It also requires a lower number of test bench simulations on the device.
Present USL waveform viewers are unable to show all of the inputs and outputs from the integrated circuit in the test bench. The waveform viewers typically contain no possibility of modifying the device inputs in a real-time (i.e., as the test is conducted) mode, requiring the device to be removed and restructured for additional testing. Therefore, there is a need for a USL waveform viewer that overcomes at least some of the disadvantages associated with conventional USL waveform viewers.